Virtually all reasonably complex embedded electrical designs consist of microprocessors and application-specific circuitry. In this model, the microprocessors typically run power-on-self-test (POST) code to test device functionality when powered on. Unfortunately, microprocessors typically have difficulty detecting electrical faults for application-specific circuitry connected to the processor bus.
In conventional devices, address-line testing algorithms generally include writing data to various locations in a device, then reading the data from the address locations to verify that the transfers were successful. Careful selection of the address locations results in high or complete address-line coverage. The algorithm works well for devices, such as random-access memory (RAM), in which all locations are fully readable/writable. Unfortunately, embedded designs typically consist of many application-specific peripheral devices whose memory map consists primarily of registers that control configuration and provide status of the device, and are not fully readable/writable.
In these devices, the only option is to look through a memory map and find a few registers that the processor can operate on or read from, to test whether the specific address lines are connected. Typically, this reduces coverage to just a few of the address lines connected to a device. In addition, it requires significant up-front work to determine which bits of which registers can be accessed for testing.
FIG. 3 shows a block diagram of a conventional microprocessor read operation. Here, the microprocessor 310 sends an address read command to an internal register 330 of embedded peripheral device 320. Internal register 330 returns a corresponding result to microprocessor 310. Based on the result, microprocessor 310 can infer whether or not the register 330 received the correct address.
As described above, however, this test can only provide an inferential result, and may not be entirely reliable.
There is, therefore, a need in the art for a circuit and method for providing a power-on self-test capability for peripheral devices that allows direct testing of address-line data.